\section{Interface}
\label{chapter 4}

In this section we describe the interface signals of each module for the different components connected to it.

\subsection{Bimodal Predictor Interfaces}


\subsubsection{Input Interface}

\begin{table}[H]
\centering
\begin{tabular}{l|p{1.5cm}|p{3cm}|p{4cm}}
\hline
\hline
Signal name & Width or Struct & Input & Description \\
\hline
\hline
clk\_i & 1 & bimodal\_predictor <- branch\_predictor & Clock for the module \\
\hline
pc\_fetch\_i & 64 & bimodal\_predictor <- branch\_predictor & Program counter at fetch stage \\
\hline
pc\_execution\_i & 64 & bimodal\_predictor <- branch\_predictor & Program counter at execution stage \\
\hline
branch\_addr\_result\_exec\_i & 64 & bimodal\_predictor <- branch\_predictor & Address generated by branch instruction at execution stage \\
\hline
branch\_taken\_result\_exec\_i & 1 & bimodal\_predictor <- branch\_predictor & Branch at execution stage is taken or not \\
\hline
is\_branch\_EX\_i & 1 & bimodal\_predictor <- branch\_predictor & Instruction at execution stage is a branch\\
\hline
\hline
\end{tabular}
\end{table}


\subsubsection{Output Interface}

\begin{table}[H]
\centering
\begin{tabular}{l|p{1.5cm}|p{3cm}|p{4cm}}
\hline
\hline
Signal name & Width or Struct & Output & Description \\
\hline
\hline
bimodal\_predict\_taken\_o & 1 & bimodal\_predictor -> branch\_predictor & Bit that encodes branch taken '1' or not '0'\\
\hline
bimodal\_predict\_addr\_o  & 64 & bimodal\_predictor -> branch\_predictor & Address predicted to jump \\
\hline
\hline
\end{tabular}
\end{table}

%--------------------------------------------------------------------------------------------

\subsection{Branch Predictor Interfaces}

\subsubsection{Input Interface}

\begin{table}[H]
\centering
\begin{tabular}{l|p{1.5cm}|p{3cm}|p{4cm}}
\hline
\hline
Signal name & Width or Struct & Input & Description \\
\hline
\hline
clk\_i & 1 & branch\_predictor <- if\_stage & Clock for the module \\
\hline
pc\_fetch\_i & 64 & branch\_predictor <- if\_stager & Program counter at fetch stage \\
\hline
pc\_execution\_i & 64 & branch\_predictor <- if\_stage & Program counter at execution stage \\
\hline
branch\_addr\_result\_exec\_i & 64 & branch\_predictor <- if\_stage & Address generated by branch instruction at execution stage \\
\hline
branch\_taken\_result\_exec\_i & 1 & branch\_predictor <- if\_stage & Branch at execution stage is taken or not \\
\hline
is\_branch\_EX\_i & 1 & branch\_predictor <- id\_stage & Instruction at execution stage is a branch\\
\hline
\hline
\end{tabular}
\end{table}

\subsubsection{Output Interface}

\begin{table}[H]
\centering
\begin{tabular}{l|p{1.5cm}|p{3cm}|p{4cm}}
\hline
\hline
Signal name & Width or Struct & Output & Description \\
\hline
branch\_predict\_is\_branch\_o & 1 & branch\_predictor -> if\_stage & Bit that encodes if the instruction being fetched is predicted as a branch\\
\hline
branch\_predict\_taken\_o & 1 & branch\_predictor -> if\_stage & Bit that encodes branch taken '1' or not '0'\\
\hline
branch\_predict\_addr\_o  & 64 & bimodal\_predictor -> branch\_predictor & Address predicted to jump \\
\hline
\hline
\end{tabular}
\end{table}